The present invention relates to a method and/or architecture for implementing a high voltage output buffer generally and, more particularly, to a method and/or architecture for implementing a high voltage output buffer with low voltage transistors.
Traditional output buffer circuits have used high voltage transistors for implementing I/Os on the same integrated circuit (IC) as low voltage transistors. Such an approach increases the technology complexity as well as the cost of implementing such a circuit.
For dual-voltage technologies, the I/Os run off a high voltage supply and the internal circuitry off a low voltage supply. Due to gate-oxide stress, low voltage transistors cannot be used in the I/Os with conventional circuits.
As transistor dimensions decrease, supply voltages have to decrease in order to prevent gate-oxide breakdown. However, in order to reduce die cost and improve performance, it is often desirable to migrate a high voltage device into a technology which is smaller, but cannot cope with the gate-oxide stress of the high voltage. A way to avoid this problem is to develop a dual voltage technology. The internals of the chip use the low voltage transistors running off a regulated power supply. The I/Os use high voltage transistors running off the high voltage main supply.
It would be desirable to implement a method and/or architecture that uses low-voltage transistors for an output buffer arranged such that the gate oxide (Gox) is not stressed above the low-voltage threshold.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first portion of an output signal in response to (i) a first supply voltage and (ii) a pullup signal. The second circuit may be configured to generate a second portion of said output signal in response to (i) a second supply voltage and (ii) a pulldown signal. The first and second circuits may be implemented with transistors that normally can only withstand the second supply voltage.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a high voltage output buffer comprising low voltage transistors that may (i) have a maximum voltage stress across gate oxide that is within the tolerance of low voltage transistors, (ii) provide an integral voltage translation from an internal low voltage stage to a high voltage output stage, (iii) be driven from a high voltage supply; and/or (iv) contain integral voltage translation from internal low voltage to external high voltage.